In local area networks, when a node joins the network, the first stream of signals it receives are connection management symbols. The symbols are especially chosen so that they can be decoded by an encoder/decoder (ENDEC) of the node without regard to their alignment within a byte of the signal stream. In a standard 5-bit/4-bit ENDEC, the start of the connection management symbols can be at any one of the 10 bits within the "byte." Decoding of these connection management symbols proceeds without regard to this alignment because of their chosen nature. However, once these symbols are processed, decoding of the data packet following these symbols requires that their "bytes" be aligned.
Typically, the required alignment was provided by the detection of a packet delimiter called a "JK" symbol-pair. Under this procedure, a preamble "byte" immediately preceding the "JK" symbol-pair could be misinterpreted; being a decoded byte.
Also, because of the manner in which an elastic buffer is used in a typical ENDEC, the elastic buffer is centered upon detection of the "JK" delimiter. During that time, a few bits in the byte-stream are dropped or added to compensate for clock differences between the upstream of local station, resulting in a non-integral number of bytes in the preamble.
For a token ring Fiber Distributed Data Interface (FDDI) networks, the physical layer has to reliably decode the incoming data stream, without any deletion or modification of frame bits. Also, the receiver is allowed to delete only few bits of IDLE for compensation of clock differences, so as to ensure a minimum number of preambles before a packet.
The physical layer of the FDDI is implemented by a combination of Encoder/Decoder (ENDEC) and fiber optic transceiver. The encoder performs repeat filter, 4B/5B encoding, parallel to serial conversion, and Non-Return to Zero (NRZ) to Non-Return to Zero Invert (NRZI) Code conversion. The decoder performs NRZI to NRZ conversion, clock recovery, serial to parallel conversion, byte alignment, 5B/4B code conversion, elasticity buffer function and line state decode.
ENDEC is implemented in Silicon by means of a two chip set called an ENDEC chip and ENDEC Data Separator. The ENDEC chip performs the encoder, control and status functions, and all the decoder functions, and line state detect function. The ENDEC Data Separator performs recovery of clock and retimes the data from the received data. In a FDDI system, there will be a plurality of ENDECs located as a token ring. In such a system each of the ENDECs have their own clock frequencies. For example, the FDDI standard requires that the clock frequency of the ENDEC is in the range of 125 Mhz+/-6.25 KHz. This 12.5 KHz range may significantly affect the information being transmitted or received unless the information received by the receive ENDEC is synchronized with the frequency of the transmitted information.
Typically, this synchronization is accomplished by deleting or adding IDLE bits of information by the receive ENDEC. The problem with this approach is that when bits are deleted from the incoming signal there is a possibility that actual data will be deleted if there are not enough IDLE bits in the incoming signal. Therefore, by deleting bits, there is a significant chance that the information may not be accurate.
Therefore, what is needed is a system for transferring information in a token ring network in a FDDI system such that the clock frequency of the data information is accurate. It is also necessary to provide a system in which the incoming data information to an ENDEC chip is synchronized without deleting any bits of information. The present invention provides such an ENDEC.